The invention relates to an input/output control apparatus for controlling an input and an output between a channel of a host computer and a device by using a cache mechanism and, more particularly, to an input/output control apparatus in which a channel adapter side and a device adapter side can asynchronously perform an input/output control.
Hitherto, as an input/output control apparatus for asynchronously execute a data transfer between a device and a channel through a cache memory, for example, there is an apparatus as shown in FIG. 1. In FIG. 1, according to a magnetic disk control apparatus 1000, channel adapter modules 1016-1 and 1016-2 are provided for channel units 1018-1 and 1018-2 of a host computer 1012, and device adapter modules 1020-1 and 1020-2 are provided for a device 1014 such as a magnetic disk device or the like. A cache function engine module 1026 and a resource manager module 1022 are provided. The resource manager module 1026 has a job table 1050. The cache function engine module 1026 has a hash table 1058. A memory of each module is constructed by a common memory 1028. In addition to a cache memory 1044, a cache allocation information region 1060 is allocated. The cache allocation information region 1060 becomes a common control information region to which the channel adapter modules 1016-1 and 1016-2 and device adapter modules 1020-1 and 1020-2 refer. Further, each module is connected by a bus, uses the cache memory 1044 on the basis of an internal command, manages data of the device 1014 on a track unit basis, and controls an input and an output.
The writing operation of the conventional apparatus of FIG. 1 will now be described. When an I/O command.cndot.write is issued from the channel unit 1018-1, the channel adapter module 1016-1 requests the cache function engine module 1026 to judge a cache status. Namely, a device logic address "CCHD" designated by the I/O command.cndot.write is converted into a hash address through a hash function and whether "CCHD" has been registered in the hash address in the hash table 1058 or not is judged. In "CCHD", "CC" denotes a cylinder address, "H" a head address, and "D" a device address. By referring to the hash table 1058, when it is judged that track data designated by the I/O command.cndot.write from the channel unit 1018-1 doesn't exist in the cache memory 1044, a writing operation for the device 1014 is executed by a control such that the device adapter module 1020-1 operates by a bypass operation for making the cache inoperative. In a reading operation of the conventional apparatus, an I/O command.cndot.read from the channel unit 1018-1 is generated and when no track data exists in the cache memory 1044 and a mishit occurs, a staging is executed from the device 1014 into the cache memory 1044 and, after that, read data is transferred to the channel unit 1018-1.
In such a magnetic disk control apparatus in which the channel adapter module and the device adapter module asynchronously operate as mentioned above, however, when a cache mis occurs on the channel adapter module side for an I/O command, it is always necessary to transmit and receive information to/from the device adapter module. There is, consequently, a problem such that there are many vain processes.
In the conventional input/output control apparatus, when an input/output command is generated from an upper channel apparatus for a defective/alternating track of the device, the same operation as that in case of an ordinary track is executed and only when the track data is actually obtained, it is possible to recognize that such a track is a defective track. Therefore, in case of a hit operation on the cache, when the track data in the cache is once read out and it is recognized that the track is the defective track and the alternating track address is obtained, an operation to again read the alternating track data from the cache memory is needed. Further, when a mishit occurs in the cache, the track data on the device is read. When the defective track is recognized and an alternating track address is obtained, an operation to again read the alternating track data from the device is needed. As mentioned above, unless the track data is read out from the cache memory or device, whether the track is the defective/alternating track or not cannot be known. The processes are complicated and need a long time by an amount corresponding to the necessity of the reading and confirming operations of the defective track data. The existence of the defective/alternating track exerts a large influence on an input/output performance. It is, therefore, demanded to make it possible to perform a caching operation similar to that for the ordinary track even in case of the defective/alternating track. An input/output control apparatus which enables a caching operation in a synonym state in the case where the same hash address as the hash address obtained by transmitting the track address through the hash function is obtained even in a different track address is demanded.
In the conventional input/output control apparatus, further, in the case where a command system of an input/output request of an upper channel unit is a CKD command system, even when requesting the continuous track data, the upper channel unit cannot declare that the input/output request is sequential. On the other hand, in case of a command system such that the upper channel unit can declare that the I/O request is a sequential access, a preceding staging process for staging from the device onto the cache can be performed. Namely, on the basis of the declaration of the sequential access, in the case where the track data exists in the cache memory, the preceding staging process such that the subsequent track data of the number which was declared by the device adapter module is staged from the device onto the cache can be executed. All of a plurality of input/output requests to the channel adapter module can be processed as hit operations at a high speed. In the CKD command system, however, since the sequential access cannot be declared, the continuous preceding staging cannot be performed. The staging is repeated one by one in response to the I/O request and it takes a long processing time. On the other hand, even in the case where the upper channel unit is based on the command system such that the sequential access can be declared, when an excessive preceding staging in which the number of continuous tracks is large is executed, there is a fear such that a busy of a device path is caused and the performance of the whole system deteriorates.